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[VHDL-FPGA-Verilog] uart_tran

Description: UART串口的传送verilog原程序，已经经过了编译仿真-Verilog UART serial transmission of the original procedure has been compiled after a simulation
Platform: | Size: 269312 | Author: 王迪 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
Platform: | Size: 338944 | Author: 韩思贤 | Hits:

[Com Port] UART

Description: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Platform: | Size: 9216 | Author: 李佳 | Hits:

[VHDL-FPGA-Verilog] fpga_uartrw

Description: FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
Platform: | Size: 55296 | Author: 蒋斌斌 | Hits:

[source in ebook] btm_communication

Description: 自己项目中用到的verilog UART程序。-Their own projects verilog UART procedure used.
Platform: | Size: 1024 | Author: liujakie | Hits:

[VHDL-FPGA-Verilog] usart_verilog

Description: Uart verilog 代码 可综合 很好的代码-Uart verilog code
Platform: | Size: 15360 | Author: shenhao | Hits:

[VHDL-FPGA-Verilog] UART_for_FPGArar

Description: it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
Platform: | Size: 5120 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] UART

Description: 自己实用Verilog编写的UART程序，1位开始位，8位数据位，1位停止位，本测试程序配置完管脚后，实用串口大师发送数据，则返回数据为发送数据+1-Verilog prepared their own UART practical procedures to start a bit, 8 data bits, 1 stop bit, the test procedure End pin configuration, the utility serial Master to send data, send data back data+1
Platform: | Size: 253952 | Author: 张键 | Hits:

[Industry research] UART_DESIGN

Description: The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
Platform: | Size: 141312 | Author: ltrko9kd | Hits:

[Software Engineering] lab3

Description: verilog source code for uart design
Platform: | Size: 546816 | Author: Krishna | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart using verilog hdl
Platform: | Size: 12288 | Author: imran ahmed | Hits:

[Software Engineering] uart

Description: UART schematic and code
Platform: | Size: 149504 | Author: buhuhubau | Hits:

[VHDL-FPGA-Verilog] UART

Description: 简易UART程序 verilog 描述-Simple UART procedure described in verilog
Platform: | Size: 18432 | Author: pan | Hits:

[VHDL-FPGA-Verilog] UART_VHDL_Verilog

Description: UART的Verilog_源码,适合初学者学习can协议。-UART s Verilog source, suitable for beginners can learn from the agreement.
Platform: | Size: 350208 | Author: lammyt | Hits:

[VHDL-FPGA-Verilog] uart

Description: This Verilog file is a desription of an UART, which is a piece of computer hardware that translates data between parallel and serial forms.
Platform: | Size: 1024 | Author: Balazs Jozsa | Hits:

[VHDL-FPGA-Verilog] sdram32

Description: DDR SDRAM source verilog source codes
Platform: | Size: 25600 | Author: sachin | Hits:

[VHDL-FPGA-Verilog] uart16450

Description: uart 16450合集,xilin altera lattice-collection of uart controller 16450
Platform: | Size: 822272 | Author: jhv | Hits:

[Other Embeded program] uart

Description: fpga 串行口 接收和发送程序，采用verilong语言编写-fpga uart ，receive and send include writed by verilog language
Platform: | Size: 371712 | Author: james | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA开发的串口通信的程序，代码是用verilog编写的，希望对大家有用！-Serial communication with the FPGA development process, the code is written in verilog and hope for all of us!
Platform: | Size: 267264 | Author: 郭富民 | Hits:

[VHDL-FPGA-Verilog] au

Description: 基于APB总线的uart控制器，包括源码和vcs脚本-UART controller based on AMBA APB
Platform: | Size: 7168 | Author: Samuel Xu | Hits:
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